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The Role
Develop and validate LVS and extraction rule decks for Intel semiconductor processes. Integrate verification flows across ICV, Calibre, and Pegasus; debug LVS issues; automate execution and reporting with scripts; collaborate with PDK, foundry, device physics, process integration, and analog design teams; and document layout implementation guidelines.
Summary Generated by Built In
Job Details:Job Description: "We are looking for a LVS Runset Development Engineer to develop and Validate LVS rule decks. The role involves working closely with PDK Team and foundry to implement LVS runsets and ensure design compliance.
Key Responsibilities:
• Rule Development: Development and QA support of LVS/extraction runset for Intel's process.
• Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between ICV, Calibre and Pegasus tools.
• Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers.
• Debug and Analysis: Provide expert-level support to design teams in debugging LVS issues.
• Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking across different design versions.
• Documentation: Maintain detailed documentation and create guidelines for designers to implement correct-by-construction layouts.Qualifications:Required Skills:
• Experience with LVS runset development.
• Familiarity with SVRF, TVF, Python or Tcl scripting.
• Strong debugging and problem-solving skills.
• Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable.
• Experience with advanced technology nodes is an advantage.
• Team player and be able to work with global teams.
Preferred Qualifications:
• Bachelor's degree with 10+ years of experience, OR
• Master's degree with 8+ years of experience, OR
• PhD degree with 2+ years of experience in LVS runset development or related field; semiconductor industry experience.
• Basic AI experience is an added skill.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Experience with LVS runset development
- Familiarity with SVRF, TVF, Python, or Tcl scripting
- Strong debugging and problem-solving skills
- Knowledge of Linux and Python, Shell, or Tcl scripting
- Experience with advanced technology nodes
- Bachelor's degree with 10 or more years of experience, or master's degree with 8 or more years, or PhD with 2 or more years in LVS runset development or a related field
- Semiconductor industry experience
- Ability to collaborate with global teams
- Basic AI experience
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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