Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:Role Overview
As a Lead Physical Design Engineer, you will drive physical design implementation for complex SoC architectures on 5nm and advanced sub-5nm technology nodes. This role requires an exceptional balance of hands-on technical execution and strategic engineering leadership.
You will own the development and implementation of P&R flows, physical verification, and timing closure, while actively driving methodology improvements and mentoring engineers across different sites and time zones to deliver high-quality silicon.
What You'll Do
SoC Integration & Technical Execution
Drive top-down/bottom-up physical design integration for complex SoC architectures on 5nm and lower nodes.
Adapt quickly to internal P&R methodologies and find opportunities to build industry best practices into existing flows.
Execute the full backend flow for block and top, from floorplanning, partitioning, and placement through CTS, routing, and extraction.
Own timing and functional ECOs, working collaboratively with signoff teams to push designs toward final closure.
Lead and mentor a small physical design team, driving block-level and top-level SoC implementation while keeping the team aligned.
Automation, Leadership & Strategy
Build and scale automation flows from scratch as needed, and optimize existing scripts to maximize design re-use.
Lead by example, setting clear execution goals, identifying technical bottlenecks early, and establishing engineering benchmarks for the team.
Drive tangible improvements in turnaround time, while elevating overall layout and design quality.
What You'll Bring
Experience & Core Expertise
15+ years of hands-on experience in physical design and backend digital flows from RTL synthesis down to final GDSII stream-out.
High proficiency in timing and physical constraints, ensuring clean translation of design intent into physical layout.
Expertise across key design stages at the SoC TOP level, with hands-on proficiency handling EDA tools for floor-planning, partitioning, placement, CTS, routing and full-chip Sign-off Physical Verification (DRC/LVS).
Tools & Automation Mastery
Deep technical expertise in advanced backend EDA toolsets, specifically across Cadence, Synopsys, and Siemens (including Genus, Innovus, Quantus, Tempus, DC, Star-RCXT, PT, PrimeRail, Voltus, and Redhawk).
Strong programming and scripting capabilities, with high proficiency in Tcl and Perl to develop robust, production-grade automation.
Soft Skills & Collaboration
Excellent analytical and problem-solving skills to independently debug complex physical and timing closure issues.
A proven track record of multi-functional collaboration, with the ability to smoothly align with teams across different geographic sites and time zones.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Skills Required
- 15+ years of hands-on experience in physical design and backend digital flows from RTL synthesis through final GDSII stream-out
- Experience implementing complex SoC architectures at 5nm and advanced sub-5nm technology nodes
- Expertise in top-level SoC physical design, including floorplanning, partitioning, placement, clock tree synthesis, routing, extraction, and signoff physical verification
- High proficiency with timing and physical constraints
- Hands-on expertise with Cadence, Synopsys, and Siemens EDA tools
- Experience with Genus, Innovus, Quantus, Tempus, Design Compiler, Star-RCXT, PrimeTime, PrimeRail, Voltus, and RedHawk
- Strong Tcl and Perl programming and scripting skills for production-grade automation
- Experience developing and optimizing physical design automation and P&R flows
- Ability to debug complex physical design and timing closure issues independently
- Experience leading and mentoring physical design engineers
- Strong cross-functional collaboration skills across geographically distributed teams and time zones
- Excellent analytical and problem-solving skills
Broadcom Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.
-
Equity Value & Accessibility — Equity grants, including RSUs, stock refreshers, and an ESPP, are often described as top-tier and a primary driver of strong total compensation, especially for technical and senior roles. Once stock begins vesting, overall pay is commonly viewed as hard for other employers to match.
-
Retirement Support — A 401(k) match of 100% up to 6% with immediate vesting is frequently highlighted as a standout benefit. This structure provides strong long-term savings support.
Broadcom Insights
What We Do
Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
