Primary Duties & Responsibilities
- Lead physical layout development for III-V semiconductor laser products including VCSELs, DFB lasers, photonic devices, and related optoelectronic technologies.
- Own layout architecture, mask design, and mask data preparation from concept through production release.
- Develop, maintain, and improve design rule methodologies, verification flows, and layout standards to ensure manufacturable and robust designs.
- Design and implement process monitor structures, test patterns, and characterization vehicles to support process development, process control, yield improvement, and reliability monitoring.
- Develop automated Design Rule Check (DRC), Layout Versus Schematic (LVS), verification, and data analysis solutions using scripting and programming languages such as Python, Tcl, Perl, or equivalent.
- Champion layout automation initiatives to improve design productivity, consistency, quality, and cycle time.
- Collaborate closely with process integration, device engineering, epitaxy, manufacturing, and product engineering teams to ensure layouts meet design, process, reliability, and manufacturing requirements.
- Drive layout reviews and cross-functional design reviews throughout product development and qualification phases.
- Support root cause investigations and failure analysis activities by evaluating potential layout-related issues and implementing corrective actions.
- Establish and maintain layout design guidelines, libraries, reusable cells, and best practices.
- Coordinate mask revisions and change management activities while ensuring configuration control and documentation accuracy.
- Lead multifunctional teams in resolving layout, manufacturability, and process integration challenges.
- Mentor layout engineering techs and provide technical guidance on layout methodologies, DRC compliance, automation, and semiconductor process interactions.
Education & Experience
- Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Physics, Materials Science, Optical Engineering, or a related technical field.
- Minimum 5 years of semiconductor layout design experience required.
- Minimum 3 years of direct experience with III-V optoelectronic devices such as VCSELs, DFB lasers, edge-emitting lasers, photonic integrated circuits (PICs), or similar technologies preferred.
- Demonstrated experience developing production mask sets and managing layout releases for semiconductor products.
- Experience designing process control monitor (PCM) structures, test keys, and process characterization patterns.
- Strong understanding of semiconductor fabrication processes and how process interactions impact physical layout and device performance.
Skills
- Expert-level experience with semiconductor layout tools, preferably Silvaco layout solutions. Experience with equivalent EDA platforms such as Cadence, KLayout, Synopsys, Mentor Graphics/Siemens EDA, or similar tools will also be considered.
- Strong understanding of physical layout design principles, mask design, DRC, LVS, and semiconductor manufacturing constraints.
Proficiency in programming and automation using Python, Tcl, Perl, C++, or similar languages. - Experience developing custom verification tools, automated design rule checks, layout generators, or workflow automation solutions.
- Hands-on experience with VCSEL, DFB laser, photonic integrated circuit (PIC), or related optoelectronic device layouts.
- Strong knowledge of lithography, etch, metallization, dielectric deposition, implantation, and other semiconductor fabrication processes.
- Familiarity with semiconductor manufacturing operations, process control methodologies, and change management systems.
- Strong analytical and problem-solving skills with the ability to evaluate complex layout-process interactions.
- Excellent communication and leadership skills with demonstrated ability to influence and drive actions across multifunctional engineering teams.
- Self-motivated and capable of leading projects in a fast-paced product development environment.
- Experience with statistical analysis tools such as JMP, Minitab, or equivalent is a plus.
Working Conditions
- Normal office environment
Physical Requirements
Work in a class 100/1000 clean room for extended periods
Wear full cleanroom attire (smock, mask, etc.)
Work with and/or around chemicals (such as solids and acids)
Stand for up to 4 hours at a time
Lift up to 16-30 Pounds
Push/Pull up to 16-30 pounds
Sit for up to 4 hours at a time
Safety Requirements
All employees are required to follow the site EHS procedures and Coherent Corp. Corporate EHS standards.
Quality and Environmental Responsibilities
Depending on location, this position may be responsible for the execution and maintenance of the ISO 9000, 9001, 14001 and/or other applicable standards that may apply to the relevant roles and responsibilities within the Quality Management System and Environmental Management System.
Culture Commitment
Ensure adherence to company’s values (ICARE) in all aspects of your position at Coherent Corp.:
Integrity – Create an Environment of Trust
Collaboration – Innovate Through the Sharing of Ideas
Accountability – Own the Process and the Outcome
Respect – Recognize the Value in Everyone
Enthusiasm – Find a Sense of Purpose in Work
Coherent Corp. is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
If you need assistance or an accommodation due to a disability, you may contact us at [email protected].
Note to recruiters and employment agencies: We will not pay for unsolicited resumes from recruiters and employment agencies unless we have a signed agreement and have required assistance, in writing, for a specific opening.
Skills Required
- Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Physics, Materials Science, Optical Engineering, or a related technical field
- Minimum 5 years of semiconductor layout design experience
- Minimum 3 years of direct experience with III-V optoelectronic devices such as VCSELs, DFB lasers, edge-emitting lasers, or photonic integrated circuits
- Experience developing production mask sets and managing layout releases for semiconductor products
- Experience designing process control monitor structures, test keys, and process characterization patterns
- Strong understanding of semiconductor fabrication processes and process interactions affecting physical layout and device performance
- Expert-level experience with semiconductor layout tools, preferably Silvaco or equivalent EDA platforms
- Strong understanding of physical layout, mask design, DRC, LVS, and semiconductor manufacturing constraints
- Programming and automation proficiency using Python, Tcl, Perl, C++, or similar languages
- Experience developing custom verification tools, automated design rule checks, layout generators, or workflow automation solutions
- Hands-on experience with VCSEL, DFB laser, PIC, or related optoelectronic device layouts
- Strong knowledge of lithography, etch, metallization, dielectric deposition, implantation, and semiconductor fabrication processes
- Familiarity with semiconductor manufacturing operations, process control methodologies, and change management systems
- Statistical analysis experience using JMP, Minitab, or equivalent
Coherent Corp. Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Coherent Corp. and has not been reviewed or approved by Coherent Corp..
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Healthcare Strength — Healthcare Strength: Health coverage includes multiple national and region-specific options (UHC HDHP/HSA, PPO, EPO; Kaiser in CA; Health Net in OR) plus separate dental (Delta Dental) and vision (VSP), indicating strong breadth and choice. This breadth supports a solid total package in certain roles and locations.
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Equity Value & Accessibility — Equity Value & Accessibility: An Employee Stock Purchase Plan allows buying shares at 85% of market price with contributions up to 10% of pay, expanding ownership access. This feature can materially bolster total rewards even when base pay is mid‑pack.
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Leave & Time Off Breadth — Leave & Time Off Breadth: Paid time off includes 15 vacation days for new hires, 10 paid holidays, and additional paid time during a December shutdown. This structure provides a clear and competitive baseline for time away from work.
Coherent Corp. Insights
What We Do
Coherent empowers market innovators to define the future through breakthrough technologies, from materials to systems. We deliver innovations that resonate with our customers in diversified applications for the industrial, communications, electronics, and instrumentation markets. Headquartered in Saxonburg, Pennsylvania, Coherent has research and development, manufacturing, sales, service, and distribution facilities worldwide. For more information, please visit us at coherent.com.








