Head of Site Reliability Engineering at ChipStack

Locations • San Jose, CA – On‑site • Full‑time • Engineering

Chips power everything, yet chip‑design tooling hasn’t kept up with the exploding complexity. ChipStack reinvents verification with AI‑native software already in use at 10+ semiconductor innovators. Backed by Khosla Ventures, Cerberus, and Clear Ventures, our small, fast team ships at the intersection of AI, EDA, and systems engineering.

We need rock‑solid, low‑latency deployments—often inside customer data centers with no internet egress. As our first dedicated reliability owner, you’ll design, automate and operate these hybrid/on‑prem environments so customers experience “five nines” availability without touching the underlying plumbing.

• Own end‑to‑end reliability – architect, deploy, and monitor production clusters (on‑prem & cloud) running our Python/TypeScript micro‑services, LLM workloads and GPU back‑ends.

• Automate the stack – build IaC pipelines (Terraform), GitOps workflows and zero‑downtime rollout strategies.

• Observe & respond – instrument apps with Prometheus/Grafana, set SLOs/SLIs, lead incident response, perform root‑cause analysis, and harden runbooks.

• Secure & comply – implement network segmentation, secrets management, RBAC and vulnerability scanning to satisfy strict semiconductor‑industry requirements.

• Collaborate – pair with product engineers on performance profiling, scalability bottlenecks and customer issue triage.

• Continually improve – champion best practices in testing, CI/CD, and chaos drills to push our “ship fast, ship quality” culture.

• 5+ years building and operating production systems as an SRE / DevOps / Platform Engineer.

• Hands‑on expertise with Kubernetes and Docker in hybrid or bare‑metal setups.

• Strong Python for automation tooling; proficiency reading TypeScript services.

• Deep Linux administration knowledge (kernel tuning, networking, storage, security hardening).

• Proven track record delivering 99.9 %+ uptime for latency‑sensitive services.

• Observability stack experience (Prometheus, Grafana, Loki / ELK, Alertmanager).

• Proficiency with Terraform (or equivalent IaC) and Git‑based workflows.

• Excellent communication and a bias for action when facing vague, first‑of‑its‑kind problems.

• Experience running GPU workloads, ML inference or EDA toolchains in production.

• Familiarity with air‑gapped / restricted‑network deployments and data‑center operations.

• Exposure to security certifications (SOC 2, ISO 27001) or semiconductor customer audits.

• Prior work at an early‑stage startup.

• Challenge status‑quo • Strong opinions, loosely held • Ship fast, ship quality • Proud of our craft

Ready to harden the infrastructure that will redefine chip design? Apply now and keep ChipStack running flawlessly for the world’s most advanced silicon teams.