Our mission is to provide real-time on-orbit connectivity for critical missions, enabling a new era of data-driven intelligence and innovation. With 33 satellites launched to date, Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities.
Key Responsibilities:
- Develop custom IP for new features of the Kepler satellite digital payloads
- Iterate on current DSP and interface designs to improve reliability
- Work with IP core vendors to integrate new functionality into the Kepler designs
- Work with lead engineers in developing the communications and network architecture of our future satellite constellation
- Participate in conceptual design studies of new spacecraft
Required Skills & Qualifications:
- Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent
- 5+ yr. working experience with FPGA/RTL design
- Verilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilog
- Xilinx FPGA(s). Specifically, Zynq and UltraScale
- Solid understanding of timing principles, including clock domain crossing and timing closure
- Strong scripting skills (e.g Python, Tcl, csh/bash, etc.)
- Experience with FPGA tools (e.g Vivado, Quartus), HDL Simulation Tools (ModelSim)
Bonus Points:
- Masters of Science in Computer/Electrical Engineering, or equivalent
- Experience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAM
- Experience with memory mapped interfaces such as AXI, Wishbone, Avalon
- Experience with high-speed transceivers for protocols such as JESD204B, PCIe, SATA
- Experience with Linting tools, Questa Sim or Riviera-Pro
- Experience with Xilinx Versal and RFSoC
- Experience designing printed circuit boards
- Knowledge of radio-frequency electronics design
Skills Required
- Bachelor's degree in Computer Engineering, Electrical Engineering, or equivalent
- 5+ years of working experience with FPGA/RTL design
- Experience with Verilog, SystemVerilog, or VHDL, with willingness to learn or pivot to SystemVerilog
- Experience with Xilinx FPGAs, specifically Zynq and UltraScale
- Understanding of timing principles, including clock domain crossing and timing closure
- Strong scripting skills, such as Python, Tcl, or csh/bash
- Experience with FPGA tools such as Vivado or Quartus
- Experience with HDL simulation tools such as ModelSim
- Master of Science in Computer or Electrical Engineering, or equivalent
- Experience with coherent digital demodulation of BPSK, QPSK, or QAM waveforms
- Experience with memory-mapped interfaces such as AXI, Wishbone, or Avalon
- Experience with high-speed transceivers and protocols such as JESD204B, PCIe, or SATA
- Experience with linting tools, Questa Sim, or Riviera-Pro
- Experience with Xilinx Versal and RFSoC
- Experience designing printed circuit boards
- Knowledge of radio-frequency electronics design
What We Do
Kepler designs, builds, launches, and operates an advanced network of low earth orbit satellites with the ultimate goal of bringing internet to outer space. Today, Kepler serves the needs of earth by connecting machines all around the world using its satellites on orbit and other complementary networks. Through a host of compatible partner equipment we make it easy to use satellite communications in your solution and route data over the best networks.








