FPGA Design Engineer

Reposted 3 Days Ago
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Los Angeles, CA
In-Office
95K-135K Annually
Junior
Software
The Role
The FPGA Design Engineer will design and implement signal processing algorithms for wireless products, participate in project research and field deployment, and support development and verification tasks.
Summary Generated by Built In

THE COMPANY

Silvus Technologies, a leading provider of advanced MANET and MIMO communications systems, is reshaping mesh network technology for mission-critical applications – on the ground, in the air, and at sea. Its battle-proven StreamCaster family of MANET radios and proprietary MN-MIMO waveform provides the vital communications link for defense, law enforcement, and public safety agencies around the world, and in the toughest operational environments.

With deep roots in DARPA research, Silvus Technologies develops world-class advanced communications technologies that are reshaping the tactical communications landscape. From pure line-of-sight to extreme non-line-of-sight, Silvus radios form a self-healing, self-forming mesh network, enabling secure and reliable connectivity, including video and high-bandwidth data

Silvus Technologies, a wholly owned subsidiary of Motorola Solutions, Inc., is part of the MSI ecosystem of safety and security technologies.

Would you like to join an incredibly talented group of people, doing very challenging work, with the prime directive of “Keeping Our Heroes Connected”?

THE OPPORTUNITY

Silvus is seeking a full-time FPGA Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team.  The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.  FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D.  These are exciting projects targeted to address challenging real-world communication needs. 

The FPGA Design Engineer will be based at Silvus headquarters in the heart of vibrant West Los Angeles, CA and is on a hybrid schedule, a minimum of 3 days onsite per week is expected. On-site days are Mondays, Wednesdays, and Thursdays.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion. 

ROLE AND RESPONSIBILITIES

  • Digital design architecting for wireless communication projects.
  • Fixed point design of signal processing blocks while working with systems engineers.
  • RTL coding, simulation, and test bench development.
  • FPGA synthesis and timing closure.
  • Hardware verification and troubleshooting; familiarity with logic analyzers.
  • Provide support to the RF and Software Engineering Teams.

REQUIRED QUALIFICATIONS

  • Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant field.
  • Minimum 2 years of demonstrated experience in FPGA design.   
  • Proven experience with multiple clock-domain, high-utilization FPGA designs.
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
  • Experience with tcl or python.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

  • Master of Science degree in Electrical Engineering (MSEE).
  • Demonstrated experience with fixed point binary arithmetic, and digital signal processing designs.
  • Basic MATLAB skill.
  • Experience with communication systems on FPGA or ASIC designs.

COMPENSATION

The pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate’s experience and qualifications.

CA Pay Range
$95,000$135,000 USD

NOTE - As a US Federal Contractor, Silvus Technologies requires that ALL candidates being considered for employment for any position (regardless of level) MUST be a U.S. Person (permanent resident or citizen).  Stricter U.S. Citizen ONLY requirements (needed for some Engineering or R&D roles) will be included in the Required Qualifications section of the posted position. This does NOT apply to international positions; only job postings for positions located in the US.

All employment is contingent upon the successful clearance of a background check and drug test.

Silvus is proud to be an equal opportunity employer, and we value diversity. We do not discriminate on the basis of race, color, age, religion or belief, ancestry, national origin, sex (including pregnancy), sexual orientation, gender identity and/or expression, marital, civil union or domestic partnership status, physical or mental disability, protected veteran status, genetic information, political affiliation, or any other factor protected by applicable federal, state, or local laws.

We will ensure that individuals with disabilities are provided with reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive benefits and privileges of employment. Please contact us to request accommodation.

*Silvus does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to Silvus Technologies.

Top Skills

Fpga
Python
Tcl
Vivado Ide
Xilinx
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The Company
HQ: Los Angeles, CA
104 Employees
Year Founded: 2004

What We Do

Founded in 2004 and headquartered in Los Angeles, Silvus Technologies develops world-class advanced communications technologies that are reshaping the tactical wireless communications landscape.

Silvus'​ revolutionary Mobile Networked MIMO (MN-MIMO) technology utilizes a proprietary blend of MIMO antenna techniques, COFDM modulation, and Mobile Ad Hoc Networking (aka mesh) to provide unmatched range, throughput, and mobility, even in the most challenging environments.

From pure line-of-sight (LOS) to extreme non-line-of-sight (NLOS), Silvus’ radios facilitate reliable duplex connectivity between 2 or more radios, forming a self-healing, self-forming mesh network that continually optimizes itself in response to changing channel conditions.

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