Company:
Qualcomm Atheros, Inc.

Job Area:
Engineering Group, Engineering Group > ASICS Engineering

General Summary:

The DV Engineer will report to a Design Verification (DV) Manager responsible for the verification of Qualcomm's Bluetooth, Bluetooth Low Energy (BT/BLE) and Ultra-Wide Band (UWB) IP for instantiation into the company's SOCs serving the company's Mobile, Automotive, Consumer, and Internet of Things business units. They will be focused on developing methodology improvements for DV but could also be assigned to help provide code coverage for Qualcomm's BT/BLE/UWB designs.

Specific Duties:

The DV Engineer may be assigned work on one or more of the following areas:

• Develop System Verilog based UVM test bench environment
• Develop a co-simulation environment to verify between C/C++ models and RTL modules
• Create testbench specifications and coverage plans Implement constrained-random sequences, agents, and environments using the UVM methodology
• Developing and maintaining complex verification environments using methodologies (UVM, SV)
• Writing test plans, creating test benches to execute those test plans, analyzing coverage and identifying and fixing test bench holes, running regressions and filing bug reports
• Devise architectures for improving multi-master, multi-slave Network on Chip (NOC) performance analysis in ASIC and FPGA design environments.
• Improve Verification coverage for power gating applications (sleep and wake sequences)
• Develop means for automating functional equivalence checking between behavioral models and underlying logic or schematic designs, emphasis on radio designs.
• Exploration of FW based testing to augment current DV techniques in ASIC design
• Improvements in monitoring functional and code coverage, including sensitivity analysis for improving coverage statistics.

Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field.

Preferred Qualifications:

• Master's degree in science, Engineering, or related field.
• Hands on experience and expert-level knowledge of advanced verification methodologies (UVM with System Verilog).
• Expert level knowledge of Coverage Driven Verification - Coverage Model design & implementation using HVLs.
• Experience in scripting languages such as PERL or Python.
• Familiarity with various power saving techniques such as clock gating and power gating.

Qualcomm is committed to hiring and supporting individuals with disabilities. Although this role has some expected physical activity, an inability to perform one or more of the listed physical requirements should not deter otherwise qualified applicants from applying. We will work with you throughout the application and onboarding process to provide reasonable accommodations. Examples of expected physical activity include: frequently transporting between offices, buildings, and campuses up to ½ mile; frequently transporting and installing equipment up to 5 lbs.; performing tasks at various heights (e.g., standing or sitting); monitoring and utilizing computers and test equipment for more than 6 hours a day; and continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

Applicants: If you are an individual with a disability and need an accommodation during the application/hiring process, please call Qualcomm's toll-free number found here for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm is an equal opportunity employer and supports workforce diversity.

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