Embedded Software (FW) Engineer

Posted Yesterday
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Reading, Berkshire, England, GBR
Hybrid
Senior level
Artificial Intelligence • Semiconductor
The Role
Design, develop, test and maintain real-time embedded firmware for high-speed heterogeneous SoC ASICs. Work on RTOS-based and bare-metal RISC-V firmware, board and SoC bring-up, FW update/secure boot, hardware interfacing, pre-silicon simulation/FPGA validation, and diagnostics for high-speed signalling (PCIe/CXL/SerDes) and retimer/AEC devices.
Summary Generated by Built In

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

We are actively seeking for an Embedded Software (FW) Engineer

Location: Reading (UK), Lausanne (CH)


Responsibility

  • Develop, test and maintain Embedded Software for Kandou AI’s new ASIC products
  • Real-time Firmware design on high-speed heterogeneous SoC platform
  • Work with Architects and Lead engineers to design and implement according to system and module specifications
  • Software design and support for our silicon design infrastructure and workflow
  • Participate in and promote current best practices in test, review, integration, automation and delivery of quality software products

Skills

  • Working with Heterogeneous multicore systems, including both scalar and vector processors
  • Real-world experience of high-speed signalling technologies: PCIe, CXL — particularly link training, equalization and retimer/redriver interaction with host and device PHYs
  • Firmware development for Active Electrical Cable (AEC) or retimer/redriver ASICs: cable diagnostics, eye margin monitoring, temperature/voltage telemetry and power-state management
  • Memory and network interfacing, virtual memory, simulation and co-simulation
  • Firmware Update approaches and algorithms
  • Use of simulation and/or FPGAs for pre-silicon development
  • Understanding of SerDes technology and PHY register-level tuning

Experience

  • 7+ years' experience in designing, coding and debugging real-time applications in C and/or C++ in an embedded environment
  • Experience in porting and use of RTOS: Zephyr(preferred), FreeRTOS etc.
  • Knowledge of RISC-V CPU architecture; experience writing bare-metal or RTOS-based firmware targeting RISC-V cores (RV32/RV64)
  • Board and SoC bring-up with JTAG and other debug mechanisms
  • FW Update, bootloaders, secure boot
  • Debugging at application, driver and hardware levels
  • Interfacing to hardware and peripherals: UART, SPI, I2C/SMBus, I3C
  • Commitment to use of modern SW development and test workflow tools (CI / GitLab / Makefile / CMake / TDD etc.)
  •  Knowledge of management and sideband protocols including SMBus, I3C, MCTP, CMIS

Skills Required

  • 7+ years designing, coding and debugging real-time applications in C and/or C++ in an embedded environment
  • Experience porting and using RTOS (Zephyr preferred) and FreeRTOS
  • Knowledge of RISC-V CPU architecture; writing bare-metal or RTOS-based firmware targeting RV32/RV64
  • Board and SoC bring-up experience using JTAG and other debug mechanisms
  • Firmware Update approaches, bootloaders and secure boot implementation experience
  • Debugging at application, driver and hardware levels
  • Interfacing to hardware and peripherals: UART, SPI, I2C/SMBus, I3C
  • Experience with heterogeneous multicore systems, including scalar and vector processors
  • Real-world experience with high-speed signalling technologies (PCIe, CXL) including link training and equalization
  • Firmware development for Active Electrical Cable (AEC) or retimer/redriver ASICs: cable diagnostics, eye margin monitoring, telemetry, power-state management
  • Understanding of SerDes technology and PHY register-level tuning
  • Use of simulation and/or FPGAs for pre-silicon development, simulation and co-simulation
  • Knowledge of memory and network interfacing, virtual memory concepts
  • Commitment to modern software development and test workflows (CI, GitLab, Makefile, CMake, TDD)
  • Knowledge of management and sideband protocols including SMBus, I3C, MCTP, CMIS
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The Company
HQ: Lausanne
222 Employees
Year Founded: 2011

What We Do

Founded in 2011, Kandou is the innovative leader in high-speed, energy efficient, chip-to-chip link solutions critical to the evolution of the electronics industry. Kandou enables a better-connected world by offering disruptive technology through licensing and standard products that empower the devices we use every day to become smaller, more energy efficient and more cost effective. Kandou has a strong IP portfolio that includes Chord™ signaling, which has been adopted into industry specifications by JEDEC and the OIF. These innovations and implementations deliver a fundamental advance in interconnect technology that lowers the power consumed and improves the performance of chip links, unlocking new capabilities for customer devices and systems. Kandou is a fabless semiconductor company headquartered in Lausanne, Switzerland with offices in Europe, North America and Asia.

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