At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
Job Title: Digital Verification Lead Engineer
Job Location: EU/UK/CH
Key Responsibilities
- Act as verification lead on projects
- Provide technical leadership & mentoring
- Prepare design verification plan based on design specifications
- Plan and schedule projects, assign and track tasks for team members
- Develop design verification methodologies and implement standard debug flows
- Participate in design reviews
- Maintain design verification environment and track & close design bugs
- Work with designers in verification and validation of circuit designs
- Utilize the latest techniques, tools, and technologies for design verification activities
Skills
- Excellent communication skills, strong team player
- Good scripting techniques, experience with regression setup & management
- Deep understanding of simulation and verification environments, including debugging techniques
- Experience with Gate Level Simulation flows and debug
- Strong knowledge on Metrics-driven verification (incl. verification planning and coverage closure)
- Experienced with test bench development using the latest methodologies
- Experience with 3rd party VIP usage and test development (a plus)
- Experience with emulation platforms and/or FPGA prototyping (a plus)
- Experience with Assertion Based Verification (a plus)
Experience
- 7+ years’ experience in the semiconductor industry
- Experience in leading and managing a team across multiple sites
- Proven track record in verifying complex designs (preferably in high volume applications)
- Skilled in trade-offs between quality and schedule
- Experience in constrained random test bench development
- Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
- Extensive digital verification background with some UVM experience
- Coordinate and oversee external sub-contractors to scale up verification workloads
Education
Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !
Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/
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What We Do
Founded in 2011, Kandou is the innovative leader in high-speed, energy efficient, chip-to-chip link solutions critical to the evolution of the electronics industry. Kandou enables a better-connected world by offering disruptive technology through licensing and standard products that empower the devices we use every day to become smaller, more energy efficient and more cost effective. Kandou has a strong IP portfolio that includes Chord™ signaling, which has been adopted into industry specifications by JEDEC and the OIF. These innovations and implementations deliver a fundamental advance in interconnect technology that lowers the power consumed and improves the performance of chip links, unlocking new capabilities for customer devices and systems. Kandou is a fabless semiconductor company headquartered in Lausanne, Switzerland with offices in Europe, North America and Asia.
