At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
Job Title: Formal Digital Verification Engineer
Location: EU/UK/CH
Key Responsibilities
- Develop formal verification methodologies and best practices
- Participate in RTL design reviews
- Prepare design verification plan based on design specifications
- Document results and coverage metrics for formal sign-off
- Plan and schedule assigned projects for timely completion
- Maintain design verification environment and track & close design bugs
Skills
- Must possess great communication skills, rigorous with an analytical mind and be a strong team player
- Good scripting techniques (python, Perl or TCL for automation), regression setup & management
- Deep understanding of Formal Verification technologies
- Strong knowledge on Metrics-driven verification (incl. test planning and coverage closure)
- Proficiency in temporal logic assertion-based languages such as SVA or PSL.
- Knowledge of traditional simulation-based verification methodologies (a plus)
- Excellent analytical, problem-solving and debugging skills
- Strong understanding of instruction-set architectures, interrupt handling and bus architectures
- Knowledge of Cadence JasperGold and VManager is preferrable
Experience
- 5+ years’ experience in the semiconductor industry
- Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC
- Skilled in trade-offs between quality and schedule
- Working with RTL design engineers to develop a formal micro-architecture specification
- Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
- Delivered reusable and optimized formal models and verification codebases to improve efficiency across project
- Experience on simulation based verification with UVM would be advantageous
Education
Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !
Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/
Top Skills
What We Do
Founded in 2011, Kandou is the innovative leader in high-speed, energy efficient, chip-to-chip link solutions critical to the evolution of the electronics industry. Kandou enables a better-connected world by offering disruptive technology through licensing and standard products that empower the devices we use every day to become smaller, more energy efficient and more cost effective. Kandou has a strong IP portfolio that includes Chord™ signaling, which has been adopted into industry specifications by JEDEC and the OIF. These innovations and implementations deliver a fundamental advance in interconnect technology that lowers the power consumed and improves the performance of chip links, unlocking new capabilities for customer devices and systems. Kandou is a fabless semiconductor company headquartered in Lausanne, Switzerland with offices in Europe, North America and Asia.
