Design Engineer II

Posted 4 Days Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop firmware for high-speed SERDES physical-layer IP across architecture, implementation, verification, validation, silicon bring-up, debugging, and customer deployment. Build prototype control software for adaptation, equalization, and control algorithms; support functional-safety compliance, post-silicon characterization, issue resolution, hot fixes, testing, and technical documentation. Collaborate with digital and mixed-signal architects, verification teams, validation engineers, product engineering, and customers.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineer II

This is an opportunity to join a dynamic and growing team of experienced engineers developing physical layer IP’s for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly motivated self-starter who can work independently to complete assigned tasks and collaborate with other members to achieve project milestones. It is expected that the candidate will contribute during all phases of firmware development for high speed SERDES - from architecture development to implementation, verification, testing and customer deployment. 

Responsibilities

  • Work closely with PHY digital and mixed signal architects to figure out the details of FW functions and sequences. Contribute during firmware architecture development and implementation of the defined firmware features.
  • Help to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.
  • Implement assigned FW features and work closely with verification[simulation] and validation team to ensure the functionality and robustness of the implemented features.
  • Support FuSa compliant firmware development. Work closely with verification and validation team to develop and execute test plans for FuSa compliant firmware.
  • Support of Validation team during electrical and system characterization during post-silicon testing. Identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.
  • Support Product Engineering, System Validation and Design team to debug IP issues during customer deployment of the IP and provide hot fixes.
  • Create and maintain comprehensive documentation related to firmware design, development, bug fixes and compliance testing.

Desired Skills

  • B.Tech with 6yrs  or M.Tech with 4 yrs in Electrical/Electronics Engineering
  • Solid programming knowledge in C/C++ and Python
  • Strong problem-solving and communication skills
  • Understanding of wireline communication principles and digital signal processing techniques is a plus
  • Knowledge in mixed signal circuit design is a plus
  • Experience with silicon validation process and debug is a plus
  • Experience with digital verification environment and tools is a plus
  • Understanding of FuSa compliance is a plus
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • B.Tech in Electrical or Electronics Engineering with 6 years of experience, or M.Tech with 4 years of experience
  • Solid programming knowledge in C/C++
  • Solid programming knowledge in Python
  • Strong problem-solving skills
  • Strong communication skills
  • Understanding of wireline communication principles and digital signal processing techniques
  • Knowledge of mixed-signal circuit design
  • Experience with silicon validation processes and debugging
  • Experience with digital verification environments and tools
  • Understanding of functional safety compliance

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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