Design Engineer II

Posted 5 Days Ago
Be an Early Applicant
Noida, Gautam Buddha Nagar, Uttar Pradesh, IND
In-Office
Entry level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop and lead reusable UVM simulation testbenches using SystemVerilog, C/C++, and RTL. Integrate formal verification and AI-driven coverage analysis, collaborate with architecture, RTL design, and software teams, and align verification plans with ISA requirements. Verify complex processor pipelines, memory subsystems, and ISA implementations while automating verification flows with Perl, Python, or Tcl and supporting processor integrations such as RISC-V or ARM with AMBA and PCIe protocols.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.


Role Overview:

 

Key Responsibilities:

  • Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
  • Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis.
  • Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

Required Qualifications:

  • B.Tech/M.Tech in ECE with
  • Experience in SystemVerilog/UVM and C/C++ for architectural modeling.
  • Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
  • Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
  • Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • B.Tech or M.Tech in Electrical and Computer Engineering
  • Experience with SystemVerilog and UVM
  • Experience with C or C++ for architectural modeling
  • Experience with processor integration, such as RISC-V or ARM
  • Experience with industry-standard protocols such as AMBA or PCIe
  • Expertise in Perl, Python, or Tcl for verification flow automation
  • Experience verifying complex pipelines, memory subsystems, or ISA implementations

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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