Design-For-Test (DFT) Engineer

Project Role : Design-For-Test (DFT) Engineer
Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.
Must have skills : Design for Testability (DFT)
Good to have skills : NA
Minimum 3 year(s) of experience is required
Educational Qualification : 15 years full time education
Summary:
As a Design-For-Test Engineer, your day involves embedding testability features into chip designs to facilitate efficient testing after manufacturing. You work closely with various teams to integrate methodologies that help identify defects early and improve overall test coverage. Your role is pivotal in ensuring the final silicon product meets quality standards by optimizing test processes and enabling precise fault detection and isolation. Collaboration and continuous refinement of test strategies are key aspects of your daily activities.

Roles & Responsibilities:
- Expected to perform independently and become an SME.
- Required active participation/contribution in team discussions.
- Contribute in providing solutions to work related problems.
- Collaborate with cross-functional teams to align testability features with design requirements.
- Analyze test results to identify potential design improvements and enhance fault coverage.
- Document test methodologies and share knowledge to support team growth and project success.
- Assist junior team members in understanding design-for-test concepts and best practices.

Professional & Technical Skills:
- Must To Have Skills: Proficiency in Design for Testability (DFT).
- Experience with scan chain insertion and optimization techniques.
- Knowledge of Built-In Self-Test (BIST) architectures and implementation.
- Familiarity with boundary scan standards and their application in chip testing.
- Ability to collaborate effectively with design and verification teams to improve test coverage and fault isolation.

Additional Information:
- The candidate should have minimum 3 years of experience in Design for Testability (DFT).
- This position is based at our BDC6F - SEZ office.
- A 15 years full time education is required.

15 years full time education

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