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Job Description:In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria
for achieving Right-first time silicon.
Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning,
partitioning, placement, clock tree synthesis, route and physical verification.
Responsibilities include, but not limited to:
• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality
Minimum Qualifications:
• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Skills Required
- MSEE or MSCS with 6 or more years of experience
- BSEE or BSCS with 8 or more years of experience
- Deep understanding of backend digital design flow
- Experience with timing and physical constraints
- Experience with floorplanning, partitioning, placement, clock-tree synthesis, and routing for SoC top-level design
- Proficiency with backend EDA tools including Genus, Innovus, Quantus, Tempus, Design Compiler, StarRCXT, PrimeTime, PrimeRail, Voltus, and RedHawk
- Proficiency in Tcl and Perl
- Experience with physical verification, extraction, ECO implementation, and STA closure
- Excellent analytical skills
- Ability to collaborate in multifunctional, cross-site, or cross-time-zone environments
Broadcom Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.
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Equity Value & Accessibility — Equity grants, including RSUs, stock refreshers, and an ESPP, are often described as top-tier and a primary driver of strong total compensation, especially for technical and senior roles. Once stock begins vesting, overall pay is commonly viewed as hard for other employers to match.
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Retirement Support — A 401(k) match of 100% up to 6% with immediate vesting is frequently highlighted as a standout benefit. This structure provides strong long-term savings support.
Broadcom Insights
What We Do
Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.









