ASIC Design/SDC Engineer

Posted 11 Hours Ago
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San Jose, CA, USA
In-Office
Senior level
Artificial Intelligence • Cloud • Information Technology • Internet of Things • Software
The Role
Develop and maintain block-level and full-chip SDCs for ASIC designs, close timing across functional and test modes, and collaborate with front-end, back-end, and DFT teams. Responsibilities include timing constraint development, clocking documentation, STA analysis, constraint quality methodologies, SDC reviews, RTL or IP integration, and mentoring design owners. The role supports next-generation networking chip development and requires expertise with industry-standard timing, synthesis, formal verification, CDC, and scripting tools.
Summary Generated by Built In

Hello,

Job Title : ASIC Design/SDC Engineer

Client: Arrow Electronics

Experience Required: 8+ years (Relevant)

Work Location: San Jose CA (Day-1 Onsite)

Visa: All visa, except H1B transfer

C2C engagements are allowed.

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.

Responsibilities include:

Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.

Option to also do block level RTL design or block or top-level IP integration.

Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.

Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.

Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.

Creating fullchip clocking diagrams and related documentation.

Minimum Qualifications

Bachelor’s Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience

Experience with block/full chip SDC development in functional and test modes.

Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus

Understanding of related digital design concepts (eg. clocking and async boundaries)

Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming

Preferred Qualifications

Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)

Experience with Spyglass CDC and glitch analysis

Experience using Formal Verification: Synopsys Formality and Cadence LEC.

Experience with scripting languages such as Python, Perl, or TCL

Skills Required

  • Bachelor’s degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience
  • Master’s degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience
  • Experience developing block-level and full-chip SDCs in functional and test modes
  • Experience with Static Timing Analysis
  • Experience with STA tools such as PrimeTime or Tempus
  • Understanding of digital design concepts, including clocking and asynchronous boundaries
  • Experience with synthesis tools such as Synopsys DC, DCG, or FC
  • Verilog or SystemVerilog programming experience
  • Experience with constraint analyzer tools such as TCM or CCD
  • Experience with SpyGlass CDC and glitch analysis
  • Experience with formal verification tools such as Synopsys Formality or Cadence LEC
  • Scripting experience with Python, Perl, or Tcl
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The Company
HQ: Redmond, WA
52 Employees
Year Founded: 2006

What We Do

WHO Founded in 2006 and headquartered in Redmond, WA. Our Senior Leadership team has more than 137 years of combined experience in the Telecommunications and Software Industry. Inabia is built on family values and close-knit culture. This commitment extends to the relationships we build with both our employees and our business partnerships. As a Minority Certified business, we strive to positively impact society through technology, people, and innovation. WHAT For over a decade, we have been providing powerful IT and business solutions to individuals and businesses alike. Here at Inabia, we believe that our success reflects our clients’ success. HOW We are fortunate to be situated in a city where technology and innovation is not only appreciated; but part of day to day lives. We are a growing company that has adapted and evolved our approach, helping us to exceed the ever-changing needs and requirements of our clients. WHY We are a company that fosters and values relationships, as a result many of our clients have been with us from the start of our journey. We ensure that our partners have access to best-in-class professional support, management consulting and staffing services. We make sure our consultants are carefully screened and selected based on their experience. This process ensures that we meet or exceed the specific needs of our clients.

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