Jobs at Graphcore

Lead a team of signal and power integrity engineers responsible for reliable high-speed connections and power delivery across AI hardware. Manage engineers, development, capacity planning, delivery commitments, analysis, hardware correlation, verification evidence, and technical investigations. Coordinate with design, firmware, test, bring-up, manufacturing, and program management teams while improving engineering methods and guiding architecture-to-bring-up decisions.

Leads a hardware design team developing power, timing, and control circuits for AI compute hardware. Responsibilities include line management, coaching, work allocation, delivery coordination, technical reviews, design documentation, issue resolution, corrective actions, and production transition. The role collaborates with systems, firmware, PCB layout, mechanical, thermal, and programme teams while ensuring circuit designs meet verification and manufacturing requirements.

Develop system-level diagnostics, stress-testing software, and validation utilities for next-generation AI SoCs. The role involves extending Arm diagnostics, testing CPUs, memory, PCIe, storage, firmware, and accelerators, debugging hardware-software interactions, automating validation across platforms, analyzing failures, and improving observability and fault isolation. Collaboration with hardware, firmware, software, and validation teams is central to supporting silicon bring-up and platform reliability.

Validate signal and power integrity for advanced compute platforms through hands-on measurement, electrical compliance testing, troubleshooting, and simulation correlation. Develop measurement plans and fixtures, measure high-speed interconnect performance, perform calibration and de-embedding, correlate results with simulations, collaborate with silicon, package, board, system, and vendor teams, and produce validation and compliance reports.

Coordinates engineering planning, schedules, milestones, dependencies, risks, issues, and delivery commitments across multiple teams. Facilitates meetings, maintains dashboards and documentation, supports resource planning, tracks actions, prepares stakeholder reporting, and improves engineering processes. The role works across geographically distributed teams and influences progress without direct authority.

Lead manufacturing engineering for hardware NPI and volume production. Provide design-for-manufacturability feedback, support contract manufacturers, improve yield, analyze production data, and resolve manufacturing issues. The role spans PCB and system design, automated surface-mount assembly, failure analysis, supplier capability, and continuous improvement. It requires close collaboration across design, test, quality, supply chain, and international suppliers, with travel to Taiwan.

Own manufacturing performance for advanced AI compute systems in volume PCB production. Improve yield, quality, manufacturability, and production processes while managing partner engineering relationships in Taiwan. Diagnose manufacturing faults, connect silicon, package, and PCB interactions, drive DfM feedback, analyze production data, and lead continuous improvement using Six Sigma, SPC, and DOE methods.

Own component backlogs and technical product roadmaps for AI compute software teams. Translate product intent into prioritized epics and stories, support sprint and PI planning, coordinate cross-team dependencies, and surface risks and trade-offs. Facilitate discussions among technical and non-technical stakeholders while helping engineering teams maintain focus and deliver meaningful outcomes across the AI compute stack.

Develop and optimise state-of-the-art machine learning models for specialised hardware and systems containing thousands of accelerators. Responsibilities include model training, benchmarking, profiling, kernel optimisation, experiment design, software testing, code reviews, and collaboration with research, software, and product teams to advance AI hardware and software. The role also involves distributed training and inference, performance analysis, and engagement with the broader AI community.

Develop, train, benchmark, and optimize state-of-the-art machine learning models across systems with thousands of accelerators. Identify performance bottlenecks, optimize kernels and software, conduct AI experiments, evaluate internal releases, and collaborate with research, software, product, and hardware teams. The role requires expertise in deep learning, hardware acceleration, performance optimization, and Python or C++ development, with desirable experience in distributed training, MLOps, LLMs, and HPC technologies.

Develop and optimize state-of-the-art machine learning models for specialized AI hardware and systems containing thousands of accelerators. Responsibilities include model training, benchmarking, profiling, kernel optimization, experimentation, software testing, code reviews, and collaboration with research, software, and product teams. The role focuses on performance, scalability, distributed training and inference, and advancing next-generation AI hardware and software.

Analyze and optimize AI training and inference workloads across distributed systems. Design benchmarks, profile performance, identify bottlenecks, and optimize communication software using MPI, NCCL, UCX, libfabric, and RDMA. Translate modeling and benchmarking results into validated system improvements while coordinating technical work across hardware, software, networking, and architecture teams.

Leads performance optimization for large-scale AI training and inference workloads across distributed systems. Builds benchmarks, profiles workloads, identifies compute, memory, networking, and software bottlenecks, and develops C++ and Python tools. Coordinates complex performance improvements across hardware and software teams, validates results with reliable data, and guides engineering decisions that improve efficiency, scalability, and reliability at data center scale.

Lead performance strategy for large-scale AI training and inference systems. Investigate workload behavior, profiling, benchmarking, modeling, distributed communication, and multi-node scaling across hardware and software. Define measurement standards, guide optimization roadmaps, review C++ and Python tools, and influence system architecture and engineering priorities across teams.

Lead a multi-site team responsible for functional post-silicon validation of AI SoCs and platforms. Plan and debug bare-metal C/C++ tests, deploy validation on first silicon, build Python automation and regression frameworks, analyze failures, improve test infrastructure, collaborate across hardware, firmware, software, and systems teams, and provide technical guidance and feedback to architects.

Lead post-silicon validation of advanced AI chips and platforms, including bare-metal C/C++ test development, first-silicon bring-up, debugging, and Python-based automated regression frameworks. Analyze failures, improve validation infrastructure and methodologies, collaborate across engineering teams, provide architectural feedback, and mentor engineers. Support software, firmware, production test, characterization, and new product introduction activities.

Lead power, thermal, and performance validation for AI compute silicon and systems across pre- and post-silicon environments. Develop validation strategies, automation frameworks, regression infrastructure, benchmark workloads, and reporting tools. Analyze performance data, debug hardware-software interactions, validate CPU, memory, interconnect, and high-speed I/O subsystems, and collaborate with architecture, firmware, software, and systems teams to improve product efficiency, reliability, and scalability.

Leads power, thermal, and performance validation for AI compute silicon and systems across pre-silicon and post-silicon environments. Develops validation strategies, automation frameworks, regression infrastructure, benchmarks, workload generators, and performance experiments. Analyzes system data, debugs hardware-software interactions, validates CPU, memory, interconnect, and I/O subsystems, and communicates findings and recommendations to cross-functional engineering teams.

Designs and validates digital hardware for Graphcore processor systems and test platforms. Responsibilities include schematic development, layout support, board bring-up, laboratory debugging, margin testing, validation planning, performance and reliability analysis, and production transfer. The role collaborates with silicon, firmware, software, architecture, and PCB CAD teams while working with processor interfaces, power delivery, clocks, resets, and server components.

Lead power-integrity engineering for high-performance AI compute systems across voltage regulation, package, PCB, and silicon. Define modelling strategies, optimize decoupling, analyze PDN impedance and transient behavior, resolve complex technical issues, and guide architecture and product decisions. Collaborate across silicon, package, board, power, systems, and validation teams while improving methodologies and mentoring engineers.