Jobs at Graphcore

Own component backlogs and roadmaps for AI compute software teams. Translate product intent into actionable epics and stories, support sprint and PI planning, coordinate dependencies across technical teams, identify risks, define acceptance criteria, and help engineers deliver aligned, high-quality outcomes.

Coordinates engineering planning, schedules, milestones, dependencies, risks, issues, and delivery commitments across multiple teams. Maintains documentation, dashboards, action logs, and operational records while facilitating meetings, reporting progress, supporting resource planning, and escalating blockers. Partners with technical and business stakeholders across distributed teams to improve communication, execution predictability, and engineering processes. Requires strong organization, communication, analytical, stakeholder-management, and project coordination skills.

Coordinate global business travel for employees, candidates, guests, and company events using online booking tools and travel agents. Arrange visas, airport transfers, expense approvals, and onboarding travel while responding to requests through shared inboxes and Slack. Support the Travel Manager with projects and provide administrative assistance to the CFO team, including training bookings, onboarding, and committee support.

Supports Graphcore’s Bristol electronics laboratories by maintaining, calibrating, troubleshooting, and configuring test equipment. The role includes ESD and laboratory safety compliance, PCB repair and modification, cable and wire harness assembly, asset and goods management, documentation, SOP development, and technical guidance for engineering teams and junior colleagues.

Coordinate manufacturing test delivery for new product introductions across chip, board, system, lab operations, and silicon characterisation teams. Build cross-functional programme plans, manage dependencies and readiness milestones, support DfX reviews, mitigate delivery risks, and improve NPI and NPD processes across globally distributed engineering and manufacturing teams.

Maintain and improve Graphcore’s cloud and on-premises networks across their operational lifecycle. Responsibilities include troubleshooting routing, switching, firewalls, Wi-Fi, and connectivity; resolving complex incidents; improving monitoring; automating routine operations; supporting upgrades and deployments; and creating runbooks and recovery procedures. The role requires hands-on experience with AWS networking, Cisco SDA or SD-WAN, large-scale L2/L3 networks, centralized firewalls, Ansible or Python, and evidence-led troubleshooting.

The Validation Chief of Staff coordinates strategic execution, planning, reporting, and cross-functional activities across silicon validation and bring-up teams. Responsibilities include tracking milestones, risks, dependencies, metrics, and technical issues; supporting leadership reviews; improving workflows and communication; coordinating distributed engineering teams; and driving process improvements. The role requires strong silicon validation knowledge, technical understanding of SoC and platform lifecycles, operational coordination, stakeholder management, Linux and Python familiarity, and occasional travel up to 25%.

Investigate next-generation AI computing architecture across rack and data-centre scales. Design experiments, benchmark AI workloads, analyze hardware-software interactions, and assess system performance, scalability, and reliability. Develop automation and tooling to collect, analyze, and visualize metrics, communicate reproducible findings, and collaborate with infrastructure, architecture, and application engineering teams.

Lead a team of signal and power integrity engineers responsible for reliable high-speed connections and power delivery across AI hardware. Manage engineers, development, capacity planning, delivery commitments, analysis, hardware correlation, verification evidence, and technical investigations. Coordinate with design, firmware, test, bring-up, manufacturing, and program management teams while improving engineering methods and guiding architecture-to-bring-up decisions.

Leads a hardware design team developing power, timing, and control circuits for AI compute hardware. Responsibilities include line management, coaching, work allocation, delivery coordination, technical reviews, design documentation, issue resolution, corrective actions, and production transition. The role collaborates with systems, firmware, PCB layout, mechanical, thermal, and programme teams while ensuring circuit designs meet verification and manufacturing requirements.

Develop and extend low-level diagnostics and stress-testing software for next-generation AI SoCs. Build configurable tools that validate CPUs, memory, interconnects, PCIe, firmware, storage, and other platform components; expose intermittent failures and silent data corruption; automate testing across server and rack-scale environments; and improve observability and fault isolation. Collaborate with hardware, firmware, software, and validation teams to support silicon bring-up, performance characterization, and platform reliability.

Develop and extend system-level diagnostics, stress-testing software, and validation tools for next-generation AI SoCs. Build configurable utilities that identify hardware failures, silent data corruption, performance issues, and reliability problems across CPUs, memory, PCIe, firmware, storage, networking, and accelerators. Collaborate with hardware, firmware, and validation teams on silicon bring-up, fault isolation, automation, observability, and platform debugging across multiple systems and silicon revisions.

Leads advanced troubleshooting, hardware bring-up, validation, and root-cause analysis for Arm-based AI compute platforms, including server blades, motherboards, power systems, and rack-scale infrastructure. Diagnoses thermal, power, networking, BIOS, and BMC issues; supports qualification and deployment; develops troubleshooting documentation; collaborates with engineering and data center teams; mentors junior staff; and participates in on-call support.

Lead advanced troubleshooting, hardware bring-up, validation, and root-cause analysis for Arm-based AI compute platforms across laboratory and data center environments. Diagnose server, power, thermal, network, BIOS, and BMC issues; support qualification and deployment of rack-scale infrastructure; develop troubleshooting documentation; collaborate with engineering and facilities teams; and mentor junior staff. Participate in on-call support during critical hardware milestones.

Defines the architecture and roadmap for shared test automation frameworks validating AI hardware platforms. Develops scalable test components, automated suites, CI/CD integrations, data pipelines, and observability tools. Leads cross-layer debugging across software, firmware, hardware, and lab infrastructure; improves test reliability, speed, and reproducibility. Partners with cross-functional engineering and manufacturing teams, establishes standards, mentors engineers, reviews designs and code, and provides Principal-level technical direction.

Develop, maintain, and release modern C++ libraries and runtime APIs for Graphcore AI hardware. Design low-level abstractions, improve performance and reliability, debug and test existing code, and own changes through implementation, integration, packaging, release, and maintenance. Create API documentation and migration guidance, support developers across the software stack, resolve integration issues, and collaborate with accelerator software and performance engineering specialists.

Lead Graphcore’s system software organization across firmware, drivers, OpenBMC, and software QA. Set strategy, priorities, plans, and delivery outcomes while overseeing platform bring-up, production releases, and long-term support. Manage managers and technical leaders, develop engineering talent, and coordinate execution across hardware, silicon, software, and product teams. Own quality, validation, automated testing, hardware-in-the-loop testing, release readiness, resourcing, dependencies, and technical risk.

Verify RTL against architecture specifications for Graphcore silicon. Responsibilities include verification planning, functional coverage closure, test generation, failure diagnosis and triage, architect feedback, shared verification infrastructure, and cross-site communication. The role requires CPU or ASIC verification experience and proficiency in SystemVerilog, Python, C++, and Linux, with leadership and planning skills.

Leads the design and delivery of complex AI accelerator SoCs, overseeing microarchitecture, RTL development, integration, implementation readiness, tapeout execution, risk management, and cross-functional collaboration. Builds and develops high-performing engineering teams while driving technical decisions, design quality, methodology improvements, and execution across the silicon lifecycle.

Develops and deploys board-level and system-level manufacturing tests for high-volume server hardware. Defines test plans, fixtures, station requirements, diagnostic coverage, pass/fail criteria, and production workflows. Partners with ODMs and cross-functional engineering teams during NPI, ramp, and sustaining production. Monitors yield, failure trends, retests, and defect escapes; leads root cause analysis and corrective actions. Supports Linux-based test environments, fixture validation, factory readiness, and continuous improvement across manufacturing operations.