Search the 87 jobs at Samsung Semiconductor, Inc.

Seeking a highly experienced SSD Test Engineer to support Enterprise and Data Center SSD products. Responsibilities include conducting compliance tests, failure analysis, test case development, and providing support at OEM sites. Requires a BS or MS in Electrical/Electronic Engineering with relevant experience and proficiency in storage protocols, programming/scripting, and team collaboration.

Join a global leader in technology to work on developing high-speed interfaces and advanced architectures. Responsibilities include analog circuit design, layout optimization, testing plans, compliance with design methodologies, and documenting designs. Requires expertise in system on chip architecture and high-speed serial interfaces.

Develop OPC correction and verification algorithms, image optimization engines, and test software at function and application level. Collaborate with developers and testing engineers to ensure software quality and performance.

Develop and implement cutting-edge Samsung modem and connectivity chips. Play a crucial role in providing RTL to GDS solution for projects. Collaborate with design teams to close timing for designs.

Manage the design engineering team at Samsung Foundry, overseeing the end-to-end chip design execution cycle and integration challenges. Required expertise in ARM architecture, chiplet-based designs, and project management. Responsible for customer interaction and team building.

Perform static timing analysis (STA) and timing optimization, generate and verify timing constraints, conducts SI/Noise analysis, and fixes timing & noise violations for SoCs at full chip/block level. Collaborate with designers for timing constraints, modify flows, and achieve timing closure. Onsite/ Hybrid position located in San Jose.

Design and implement advanced visualization tools for AI/ML applications, collaborate with cross-functional teams, troubleshoot and provide technical support, and stay updated on visualization tools trends.

Staff Engineer position at Samsung Semiconductor Inc. focusing on process integration for DRAM technology development. Responsibilities include planning, designing, and implementing process integration, defining technology requirements, engaging with cross-functional teams, and analyzing data for performance improvement.

Samsung Semiconductor is seeking a Senior Staff Engineer with 15+ years of industry experience to lead process integration for DRAM technology development. Responsibilities include defining technology requirements, executing technology integration activities, engaging with cross-functional teams, and analyzing data for performance improvement. The role is hybrid, with 3 days onsite in San Jose and remote work flexibility.

Responsible for requirements, design, integration, and verification of GNSS Software solution. Collaborate with engineering teams for optimization and performance enhancement. Provide SW architecture, algorithms, and trade-offs for Performance and Power. Required travel to SJ and Korea. Proficient in C, Matlab, Python.

Develop CMOS technology for next generation DRAM technology, collaborate with various teams for device optimization, analyze data for improvement, and contribute to the growth of Samsung's memory business.

The Senior Manager of Layout Design at Samsung Semiconductor Inc. will be responsible for growing Samsung’s memory business, building technology leadership, and market opportunities. They will drive high quality physical layout design projects, manage project tasks, develop critical custom digital/analog blocks, lead the physical layout team, collaborate with process integration and design engineers, support test element group layout, and customize DRCs for next technology development.

Passionate Talent Acquisition Coordinator needed to facilitate a smooth and delightful candidate experience, manage talent tools, and support the growth of high-performing teams in a global tech company.

Senior Staff Engineer role at Samsung Semiconductor focusing on signal integrity and analog design. Responsibilities include obtaining design material properties, building 3D models, simulating circuit performance, and designing wireline communication circuit components. Requires 15+ years of experience, strong teamwork and communication skills, and a proactive and innovative mindset.

Collaborate with industry open ecosystem leaders to develop SPDK features, participate in the SPDK open-source community, debug and fix issues, and support internal teams using SPDK. Position is located in San Jose, CA and offers a hybrid work environment.

The Manager, NAND/SSD Field Application Engineer will be responsible for managing technical accounts for NAND solutions and maximizing sales contribution.

Manage the balance of quarterly demand forecast against the supply plan, establish customer allocation based on priorities, monitor demand trends, and analyze demand forecast and supply against objectives. Work closely with headquarters to optimize demand balance and revenue. Bachelor's degree and 10 years of experience preferred.

Design and develop software for a state-of-the-art distributed storage system focusing on performance, scalability, and reliability. Collaborate with cross-functional teams to ensure exceptional storage solutions. Hybrid work model with onsite presence in San Jose 2-3 days per week. Requires 10+ years of C/C++ development experience in Linux environment and expertise in algorithms & data structures.

Design and optimize storage (SSD) controllers for emerging technology applications, focusing on SoC physical design and synthesis processes. Collaborate with teams to ensure high-quality design meets PPA goals. Requires a Bachelor's/Master's/PhD in Electrical/Computer Science, 5+ years of industry experience, and proficiency in Python.

Define memory controller level hardware architecture, design requirements, and implement RTL code. Collaborate with teams to optimize system performance, area, and power. Ensure timing closure and functional coverage criteria are met. Deep understanding of flash memory controller architecture and storage technologies is required.