Responsibilities
- Define overall verification strategies, methodologies, and simulation environment
- Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.
- Develop, maintain and publish verification specifications.
- Analyze and debug simulation failures
- Generates code coverage and functional coverage report
- Run gate level simulation and debug them.
- Perform the constraint assertion-based verification
Qualifications and Skills
- BS in EE with 3+ years of experience or MS in EE with 1+ year experience
- Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
- Fluent in verification language such as UVM/OVM/System Verilog, Vera, Verilog
- Experience in writing Test-plans and creating directed and random test cases
- Strong scripting skills in Perl, Python, Linux shells etc.
Top Skills
What We Do
Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores in advanced FinFET nodes to 28nm, that enable differentiated systems-on-chip (SoCs) in applications ranging from 5G, wireline and optical communications, LiDAR, radar, networking, AI, image sensors, and IoT. Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few Msps to over 20 Gsps sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins, Colorado, Boston, Massachusetts and Bangalore, India.
.jpeg)
