We are hiring a Senior DFT Engineer in Europe to own Design-for-Test on customer SoCs end-to-end: DFT architecture, scan/ATPG, memory BIST, boundary scan, pattern validation and production test hand-off.
The company provides end-to-end ASIC and COT design and turnkey manufacturing services to fabless companies and OEMs building advanced SoCs. Its offering covers architecture, RTL-to-GDSII implementation, analog/mixed-signal design, and productization through silicon, package, and test. Working across process nodes from 180nm to 2nm, it has completed over 350 tape-outs since 1986
RequirementsMust-Have Requirements:
- BSc in Electrical Engineering from a recognized university.
- Minimum 3 years of hands-on DFT experience — must. Senior-level profiles preferred.
- DFT methodologies: scan, ATPG, at-speed test, memory BIST, I/O DFT.
- Scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ fault models; test-coverage improvement.
- DFT DRC analysis and coverage debug with Synopsys DFT Compiler / TestMAX (TetraMAX) / SpyGlass DFT or equivalent Siemens (Mentor) Tessent tools.
- Memory BIST — Tessent MBIST.
- Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6 and IEEE 1500 (formerly P1500).
- Hands-on design and implementation of DFT features.
- End-to-end DFT flow ownership: concept → tape-out → production.
- Gate-level simulation setup and runs (pattern validation).
- Formal equivalence checking.
- Perl / Tcl / UNIX scripting for flow automation.
Nice to Have
- Broader Siemens Tessent experience (ScanPro / TestKompress, LBIST) beyond MBIST.
- Advanced-node experience (7nm and below).
- Python for flow automation.
Skills Required
- Bachelor of Science degree in Electrical Engineering from a recognized university
- At least 3 years of hands-on DFT experience
- Experience with scan, ATPG, at-speed test, memory BIST, and I/O DFT methodologies
- Experience with scan insertion and ATPG for stuck-at, transition-delay, bridging, and IDDQ fault models
- Experience improving test coverage
- Experience with DFT DRC analysis and coverage debugging
- Experience with Synopsys DFT Compiler, TestMAX, TetraMAX, SpyGlass DFT, or equivalent Siemens Tessent tools
- Experience with Tessent MBIST
- Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6, and IEEE 1500
- Hands-on design and implementation of DFT features
- End-to-end DFT flow ownership from concept through tape-out and production
- Experience setting up and running gate-level simulations for pattern validation
- Experience with formal equivalence checking
- Perl, Tcl, and UNIX scripting for flow automation
- Senior-level DFT experience
- Broader Siemens Tessent experience, including ScanPro, TestKompress, or LBIST
- Experience with advanced process nodes of 7nm or below
- Python for flow automation
What We Do
Commit is a global tech services company with offices in Israel, US, Canada, UK, and Europe. The company was founded in 2005 and has over 700 multi-disciplinary innovation experts who serve a broad range of companies, from small startups to large enterprises in multiple business sectors. Commit specializes in advanced technologies and applications with dedicated practices in Cloud, GenAI, Software, IoT, Big Data, Cyber, Collaboration, Data center migration projects, and more. Commit offers innovative, end-to-end technology solutions by developing custom software and IoT platforms for clients looking to build their next-gen products within the modern ICT world. Commit’s complete and comprehensive engineering powerhouse of resources, and proprietary Flexible R&D methodology helps transform its clients’ technology visions into high-quality products while reducing costs and improving time-to-market.
