Essential Duties and Responsibilities:
- The primarily responsible for design of advanced semiconductor packages, including both ceramic and organic substrates, including layout, parasitic extraction, and optimization
- Work with IC design, system design, package Signal Integrity (SI)/Power Integrity (PI) & thermal engineering teams to design custom interposer and substrates
- Work with SoC design teams to optimize die floorplan, bump patterns and interposer / substrate stack up
- Work with IC design team to define IC package requirements
- Design package layout using standard CAD tools
- Extract package parasitics and conduct PI/SI analysis
- Documentation and release in appropriate archival system
Preferred Knowledge, Skills, And Abilities
Layout:
- Allegro Package Designer Plus (APD+) tools for designing the package and generating artwork for fabrication.
Analysis:
- Celsius PowerDC (IR Drop)
- Sigrity Advanced SI II: Analysis tools for Signal integrity of parallel busses ( DDRx) and serial links (PCIe Gen x), including Package and PCB effects
- Sigrity Advanced PI II: Power Integrity tools ( IR drop, Impedance Profile, capacitor optimization) including Package and PCB effects
RF / Microwave Design
- AWR, Momentum and HFSS Software Circuit, system, and EM simulation for RF/microwave product development
Qualifications
- Bachelors degree in Electrical Engineering, Mechanical Engineering, or other semiconductor packaging related discipline.
- 8 to 10 years of experience in semiconductor packaging design, modeling, and simulations
- Strong authority on Cadence Allegro Package Designer Plus (APD+)
- Experience on interposer and substrate layouts and design in advanced package technologies
- Experience with 2.5D, 3D package design
- Experience with design teams on floor plan, bump and layout optimization
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
- Record of success in cross-functional team environment
- Good experience with SI/PI tools for package level extraction/simulation
At Micross, our Core Values of integrity, communication, teamwork, quality and execution, self-discipline and accountability are cultivated throughout all levels of the organization. Micross provides a challenging and enjoyable workplace for members and supports the needs of the community.
Micross provides competitive benefits including medical, HSA and FSA plans, dental, vision, company paid basic Life Insurance, Employee Assistance Program (EAP), 401k with employer match, paid leave, vacation, holidays, generous tuition assistance, 529 College Savings, Pet insurance, Legal insurance, and a range of well-being programs available.
www.Micross.com
Qualifications Behaviors Required Team Player: Works well as a member of a group Thought Provoking: Capable of making others think deeply on a subject Preferred Detail Oriented: Capable of carrying out a given task with all details necessary to get the task done well Education Required Bachelors or better. Equal Opportunity Employer
This employer is required to notify all applicants of their rights pursuant to federal employment laws. For further information, please review the Know Your Rights notice from the Department of Labor.
Skills Required
- Bachelor’s degree in Electrical Engineering, Mechanical Engineering, or a semiconductor packaging-related discipline
- 8 to 10 years of experience in semiconductor packaging design, modeling, and simulations
- Strong proficiency with Cadence Allegro Package Designer Plus (APD+)
- Experience with interposer and substrate layouts and advanced package technologies
- Experience with 2.5D and 3D package design
- Experience optimizing floorplans, bump patterns, and package layouts with design teams
- Experience with signal integrity and power integrity tools for package-level extraction and simulation
- Excellent problem-solving, written and verbal communication, organization, and self-motivation skills
- Successful experience working in cross-functional teams
- Knowledge of Celsius PowerDC, Sigrity Advanced SI II, and Sigrity Advanced PI II
- Knowledge of AWR, Momentum, and HFSS for RF/microwave simulation
- Detail-oriented approach to completing tasks
What We Do
Micross is the leading global one-source, one-solution provider of Bare Die & Wafers, Advanced Interconnect Technology, Custom Packaging & Assembly, Component Modification Services, Electrical & Environmental Testing and Hi-Rel Products to manufacturers and users of semiconductor devices. In business for over 40 years, our extensive hi-reliability capabilities serve the global Aerospace & Defense, Space, Medical, Industrial and Fabless Semiconductor markets. Micross possesses the sourcing, packaging, assembly, engineering, test and logistics expertise needed to support an application throughout its entire program cycle. www.micross.com Micross' Advanced Test Facility, Silicon Turnkey Solutions (STS), located in Milpitas, CA is an industry-recognized collaborative partner that integrates design, engineering, manufacturing and qualification processes with operational expertise to provide leading edge technology and test services that enable customers to meet demanding time-to-market pressure, cost and technical challenges. Micross STS possesses more than 25 years of electronic test expertise. For additional information, visit www.sts-usa.com
