[Permanent position] Senior IP subsystem SoC architect

Posted Yesterday
Be an Early Applicant
6 Locations
Hybrid
Senior level
Hardware • Information Technology • Semiconductor
The Role
Define and drive IP, subsystem and SoC architectures; decompose architectures into functional blocks and specs; select commercial IP and process technologies; define software/configuration interfaces; support RTL, physical design, verification and prototyping teams; review microarchitecture and validation plans; liaise with product/marketing and external partners; lead work packages, coordinate deliverables, and mentor junior engineers.
Summary Generated by Built In
❓ About SiPearl…

SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint.

In June 25, SiPearl completed the design of the most complex CPU ever designed in Europe, Rhea1. Featuring 80 Arm Neoverse V1 cores, with 61 billion transistors, it is currently in production at TSMC. Sipearl CPUs will equip the two first European exascale supercomputers belonging to EuroHPC JU: Rhea1 will be integrated into the JUPITER machine based in Germany and Rhea2 will be part of Alice Recoque in France.

Incubated within the European Processor Initiative (EPI) consortium and seed-funded by the European Union, SiPearl employs almost 200 people in :

  • France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis),

  • Spain (Barcelona)

  • and Italy (Bologna)

Following a €130 million Series A, the company has launched its Series B round.

💻 About the role

In this role, you will work closely with the Design, Verification, Physical Implementation and Software teams to define, drive and evolve IP, subsystem and SoC architectures aligned with performance, cost, manufacturability and market requirements.

You will act as a technical authority and architectural reference, contributing to strategic decisions, cross-team alignment, external partnerships and team development.

🎯About the missions
  • Define IP, subsystem and SoC architectures to meet performance, silicon area, cost and manufacturing constraints

  • Break down architectures into functional sub-blocks and write high-level architecture specifications, including interfaces and configuration mechanisms

  • Participate in commercial IP selection and process technology choices

  • Provide detailed definitions of software programming and configuration interfaces

  • Support RTL, physical design, verification, virtual and software prototyping teams by clarifying architectural intent and constraints

  • Review microarchitecture specifications, verification strategies and validation plans

  • Interface closely with marketing and product teams to ensure architectural alignment with roadmap and customer needs

  • Contribute to technology intelligence, monitoring standards, market trends and emerging technologies

  • Represent the company at seminars, conferences and technical forums, and share key learnings internally

  • Take ownership of work packages in collaborative and partnership projects, acting as a technical point of contact

  • Coordinate project deliverables and contribute regularly to partner exchanges

  • Mentor, coach and technically supervise junior engineers, trainees and service providers

  • Contribute to effort estimation, milestone planning, onboarding and training programs

  • Support the manager in supervising team members within the defined scope

🔍 What will help you succeed in this role
  • Extensive experience in complex chip architecture and microarchitecture

  • Strong background in electronic engineering, microelectronics or computer engineering

  • Ability to translate market and product requirements into robust technical architectures

  • Excellent communication skills, with the ability to explain complex concepts to diverse audiences

  • Strong leadership, mentoring and cross-functional collaboration skills

  • High level of autonomy, accountability and strategic thinking

  • Professional proficiency in English in an international environment

  • Scientific rigor, attention to detail and strong analytical capabilities

➕ Experience in the following areas is a strong plus
  • Core architecture design, PCIe, UCIe, memory interfaces

  • Cache architectures, memory consistency models, Network-on-Chip (NoC)

  • Communication protocols and system-level integration

  • Advanced ASIC design flows and semiconductor technologies

  • Strong software background and hardware/software co-design

  • Proficiency in scripting languages (Python, TCL, etc.)

  • Leadership roles in collaborative or multi-partner projects

Dear candidate, even if you consider you do not fulfill all the qualifications mentioned above, please still apply and share with us why you believe you would be a good fit.

Recruitment process

✔️Discovery interview with our Talent Acquisition Partner (30 min)

✔️AssessFirst personality test - no need to worry, there is no wrong or right answer; our goal is to see beyond your resume (45')

✔️2 Technical interviews (1h each)

✔️Interview with one HRBP in order to answer to your last questions (30 min)

💡 Benefits and conditions
  • Contract: Permanent Contract

  • Benefits: annual bonus*; meal vouchers (60% covered by SiPearl); health insurance (70% covered by SiPearl); illimited access and pre-paid sessions with a practitioner of your choice on our mental health partner app, moka.care; technical, linguistic and personal development training; BSPCE

  • Work model: On-Site or Hybrid (2 days/week remote)

  • 📍 Office: This role is open for our locations in France (Maisons-Laffitte, Massy, Grenoble and Sophia Antipolis), Spain (Castelldelfels - Barcelona), Italy (Bologna)

  • ⚠️ Please note that while we do not provide VISA Sponsorship, we are committed to assisting international candidates with the visa application process to the best of our ability.

Are you curious to learn more about us?

  • Follow us on LinkedIn to stay updated with our latest news

  • Get updated about our recruiting activities: Sipearl careers webpage

  • Get to know a bit more about our team culture: Welcome to the jungle

At SiPearl, we are dedicated to building a diverse and inclusive workplace that thrives on the strength of varied perspectives and backgrounds. We recruit talent based on merit, experience, and alignment with our company's goals and values.

Skills Required

  • Extensive experience in complex chip architecture and microarchitecture
  • Strong background in electronic engineering, microelectronics or computer engineering
  • Ability to translate market and product requirements into robust technical architectures
  • Excellent communication skills with diverse audiences
  • Strong leadership, mentoring and cross-functional collaboration skills
  • High level of autonomy, accountability and strategic thinking
  • Professional proficiency in English
  • Scientific rigor, attention to detail and strong analytical capabilities
  • Core architecture design
  • PCIe
  • UCIe
  • Memory interfaces
  • Cache architectures and memory consistency models
  • Network-on-Chip (NoC)
  • Communication protocols and system-level integration
  • Advanced ASIC design flows and semiconductor technologies
  • Strong software background and hardware/software co-design
  • Proficiency in scripting languages (Python, TCL)
  • Leadership roles in collaborative or multi-partner projects
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The Company
200 Employees
Year Founded: 2019

What We Do

SiPearl is a European fabless semiconductor company designing sovereign, secure, high-performance and energy-efficient CPUs for high-performance computing, artificial intelligence and data-center applications. Founded with European Union support, it develops processor technology intended to strengthen Europe’s control over the technological core of supercomputers. Its mission centers on delivering advanced compute hardware for demanding scientific, industrial and digital infrastructure workloads.

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