CPU Design Architect / Principal Digital Design Engineer

Reposted 2 Months Ago
Be an Early Applicant
Sunnyvale, CA, USA
In-Office
Senior level
AdTech • Computer Vision • Machine Learning • Software
The Role
Design and optimize CPU architectures, integrating advanced performance features while leading research on CPU design technologies and methodologies.
Summary Generated by Built In

Job Description:
Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in: 
- Perform CPU development and design integration for MIPS CPU subsystem.  
- Explore latest technologies and be responsible for conducting fundamental research on new directions in CPU architecture  
- Contribute ideas for advanced CPU performance features - analyze workloads in details, identify performance bottlenecks and opportunities, bring a data driven approach to tradeoffs in CPU design, derive architecture and micro-architecture to design/model implantation team, and bring ideas to successful silicon

Minimum Qualifications: 
- Master Degree in Electrical Engineering, Computer Science or Computer Engineering. 
- At least 5 years of CPU related Architect/RTL/Verification/Implementation design experience  
- Knowledge and practical experience with common RISC CPU architecture. 
- Familiarity with chip digital design flow, including RTL integration, simulation, STA. 
- Understanding of high performance techniques and trade-offs in a CPU microarchitecture  
- Ability to problem solve and prove own ideas 

Preferred Qualifications: 
- PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS 
- 8+ years of CPU related Architect/RTL/Verification/Implementation design experience  
- Strong CPU architecture knowledge and micro-architecture knowledge  
- Familiarity with Symmetric Multi-processing (SMP) and Snoop-based multi-processor architecture. 
- Familiarity with synthesis, power analysis and post silicon debugging 
- Cross-site working experience is a PLUS. 
- Common knowledge in modeling/DV/OS is a PLUS. 
- Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.

#LI-DNI

Skills Required

  • Master Degree in Electrical Engineering, Computer Science or Computer Engineering
  • At least 5 years of CPU related Architect/RTL/Verification/Implementation design experience
  • Knowledge and practical experience with common RISC CPU architecture
  • Familiarity with chip digital design flow, including RTL integration, simulation, STA
  • Understanding of high performance techniques and trade-offs in a CPU microarchitecture
  • Ability to problem solve and prove own ideas
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The Company
HQ: Sunnyvale, CA
232 Employees
Year Founded: 2014

What We Do

Located in the heart of Silicon Valley, Baidu USA is one of the R&D centers of Baidu, China’s largest search engine provider. Baidu USA’s team of elite, world-class researchers and engineers devote their time to tackling the most challenging, change-the-world projects in AI and related fields. Baidu USA is comprised of four groups: Baidu Research US, Intelligent Driving Group US, Baidu USDC and Smart Living Group US. At Baidu USA, we act with the nimbleness of a startup, but as a global company, have access to immense computing resources and data. This makes Baidu USA the best place for those working in AI to see their work developed and potentially deployed to hundreds of millions of users. The name Baidu was inspired by a poem written more than 800 years ago during China's Song Dynasty. Baidu, whose literal meaning is “hundreds of times,” represents a persistent search for the ideal.

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