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Looking for a Senior Design Verification Engineer with 8 or more years of experience in hardware development. Responsibilities include verifying complex design blocks using SV/UVM, developing test plans, debug regression fails, and more. Must have strong communication skills and be comfortable working across geographies.
Seeking a Senior Design Verification Engineer with 8+ years of verification experience in hardware development using SystemVerilog and UVM methodologies. Responsibilities include verifying complex design blocks, developing test plans, and debugging regression fails. Bachelor's or Master's degree in related field required.
Design Verification Engineer role at Correct Designs involving verifying complex design blocks, executing pre-silicon verification test plans, developing verification components, and debugging regression fails. The position requires 3+ years of verification experience with strong skills in SystemVerilog and UVM methodologies.
Seeking Design Verification Engineers with 3+ years of experience in SystemVerilog and UVM verification methodologies. Responsibilities include verifying complex design blocks, developing pre-silicon verification test plans, and debugging regression fails. Must have a Bachelor or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
Looking for a Senior Formal Hardware Verification Engineer with 8+ years of experience in a hardware development setting. Must have strong background in formal verification methodologies and experience with tools such as Cadence Jasper, Mentor Quest FV, and Synopsys VC Formal. Responsibilities include verifying complex design blocks using formal verification methods, developing and executing test plans, developing verification tools, and debugging regression fails. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science required.