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The Principal PHY/MAC RTL Design Engineer will be responsible for implementing MAC and PHY algorithms for low power IoT connectivity devices, developing specifications, creating micro-architecture in Verilog/Systemverilog, verifying designs, and collaborating with cross-functional teams.

As a PHY Verification Engineer/Lead at InnoPhase IoT, you will define and develop UVM testbenches for wireless PHY and MAC layers, collaborating with design and system engineers. Responsibilities include optimizing test plans, conducting verification coverage analysis, running regressions, and refining verification tools. Your role also involves debugging and problem-solving in a team environment.

As a PHY Design Engineer/Lead, you will be responsible for developing low-power WiFi and BT/BLE micro-architecture and RTL design. You will work on digital signal processing engines, analyze design bottlenecks, and collaborate with verification teams on test plans and design tools.