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The Senior Performance Software Engineer will evaluate performance bottlenecks in GPU applications, create performance metrics and micro benchmarks in both cloud and bare metal environments, and collaborate with other specialists to tackle engineering tasks. Advanced knowledge of computer architecture and strong coding skills in Python and C/C++ are required.

The Senior Mixed Signal Design Engineer will develop high-speed interfaces and analog circuits, from concept through silicon characterization. Responsibilities include schematic design, circuit verification, and post-silicon debugging, using tools such as Cadence and Spectre.

The engineer will verify the design and implementation of leading GPUs and Mixed Signal CMOS circuits, developing verification infrastructure, and collaborating with multi-functional teams to ensure design correctness.

The role involves developing test methodologies for photonic designs, conducting validation and characterization of new optical and mixed-signal designs, and providing feedback to designers on performance. It requires collaboration with multi-functional teams and training new engineers.

As a Senior Mixed-Signal/Analog Circuit Designer, you will develop high-speed IC interfaces and complex analog functions, design mixed-signal circuits in deep sub-micron CMOS technologies, collaborate with physical/layout engineers, and support silicon lab characterization. Strong experience with digital links, analog circuit concepts, and proficiency in scripting and design tools is required.

As a Senior Memory System Architect at NVIDIA, you'll lead architecture development for memory systems, optimizing performance and efficiency. Responsibilities include analyzing benchmarks and workloads, debugging performance issues, and collaborating with teams to deliver high-quality memory solutions for advanced computing applications.

As a Senior Mask Layout Design Engineer, you will collaborate with a multidisciplinary team to perform physical layout for mixed-signal functions in sub-micron CMOS technologies, using Cadence tools. Responsibilities include custom layout, verifying against design rules, and interacting with foundries.