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The Data Center Engineer is responsible for optical testing, hardware replacement, cabling, troubleshooting, and ensuring optimal data center operations.

The role involves developing and validating ASIC hardware, coding device drivers, creating automated test frameworks, and collaborating with engineers to ensure quality standards.

As a Senior AI Compiler Engineer, you will design and build a custom MLIR-based compiler stack for next-gen silicon, optimizing AI models without an OS. Responsibilities include creating MLIR dialects, ensuring accuracy in lowering computational graphs, and maintaining a high-performance compiler codebase.

The Principal RTL Methodology Architect will lead the development of scalable frontend design methodologies, ensuring high RTL quality and implementing AI enhancements in silicon design.

The ASIC RTL Design Engineer will design and verify RTL for complex ASICs, collaborating on cross-functional initiatives and optimizing circuits from specification to silicon.

As an ASIC Design Verification Engineer, you'll develop verification environments for 5G ASICs, focusing on TLM modeling, testbench architecture, and debugging RTL at the block and chip levels.

Lead a team of verification engineers ensuring top-level verification of ASIC designs, while collaborating with various teams to enhance processes and strategies.

The ASIC Backend Design Manager will lead a team of backend engineers in driving synthesis and backend functions, ensuring alignment with global priorities and delivering quality silicon for 5G networks.

The Principal AI Model Architect's role includes optimizing model architectures for new hardware, translating AI algorithms into hardware specifications, and projecting performance for silicon design.

The Principal AI Compiler Engineer designs hardware for AI, ensuring models translate effectively to silicon and perform optimally in 5G applications.