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Architect, design, integrate, test, qualify, and support GPS receivers for military weapons applications. This onsite systems engineering role spans the full development lifecycle, including requirements management, system design, test development, integration, qualification, and customer support. The engineer will collaborate with cross-functional teams, apply systems engineering processes, and develop advanced navigation solutions for defense applications.

Develop automated test software and systems for GPS receivers, anti-jam systems, and navigation products. Build C# and C++ test solutions using NI TestStand, integrate laboratory instrumentation and PXI hardware, and support functional, environmental, boundary scan, and communication-interface testing. Troubleshoot complex test issues, collaborate with design and operations teams, provide technical guidance, and optimize test architectures and product transitions.

Leads and scales a space systems engineering team developing satellite and orbital PNT solutions. Responsibilities include recruiting, mentoring, performance management, MBSE and digital engineering adoption, AI workflow integration, technical execution, space-qualified design guidance, requirements and architecture development, verification, and collaboration with program management and business development. The role requires systems engineering leadership, strategic technical direction, and organizational growth in a hybrid environment.

Leads architecture, design, implementation, integration, verification, and documentation for real-time embedded GPS receiver software used in military applications. Analyzes requirements, defines interfaces, mitigates technical risks, supports demonstrations and customers, develops tools, conducts code reviews, mentors engineers, and provides technical leadership throughout the software lifecycle.

Leads strategy, integration, governance, and operational coordination for Environmental Effects Engineering across internal and third-party laboratories. Responsibilities include expanding EMI/EMC, dynamics, and climatics capabilities; standardizing documentation and quality systems; developing performance metrics; coordinating resources and work packages; planning laboratory expansion; and building capital investment cases. The role requires engineering laboratory leadership, military environmental and EMI/EMC testing knowledge, and project management of budgets and schedules.

Designs and supports FPGA systems across the full development lifecycle, including requirements, architecture, RTL coding, synthesis, place-and-route, timing closure, simulation, lab testing, debugging, and product support. The role requires VHDL or Verilog, FPGA tools, high-speed interfaces, static timing analysis, clock-domain crossing expertise, revision control, scripting, and hardware debug. The engineer will work onsite, collaborate with verification teams, mentor others, and may lead design activities.

Designs and supports FPGA hardware through requirements, RTL coding, synthesis, place and route, timing closure, simulation, lab testing, debugging, and product support. The role requires experience with FPGA or ASIC development, HDL coding, high-speed interfaces, revision control, scripting, and hardware verification. It is fully onsite, requires U.S. citizenship, and requires a current Secret clearance or eligibility to obtain one.

Leads an FPGA design engineering team through requirements development, architecture, RTL coding, synthesis, simulation, testing, lab debugging, and product support. Provides technical oversight, mentoring, and design-team leadership while developing FPGA solutions using VHDL or Verilog. The role requires expertise in timing-driven design, clock-domain crossing, high-speed interfaces, FPGA development tools, digital simulation, and government-cleared defense electronics programs. Full-time onsite presence is required.

Designs and supports FPGA systems through requirements, architecture, RTL coding, synthesis, place-and-route, timing closure, simulation, laboratory testing, debugging, and product support. The role requires expertise in FPGA or ASIC development, HDL coding, high-speed interfaces, timing analysis, revision control, scripting, and hands-on hardware debug. Responsibilities may include mentoring engineers, modifying legacy designs, supporting verification teams, and leading design activities. This is a full-time onsite defense role requiring Secret clearance or eligibility.

Develop and lead FPGA design verification for electronic warfare systems. Responsibilities include architecting SystemVerilog, UVM, OVM, or VHDL testbenches; creating constrained-random test plans; analyzing coverage; developing reusable verification IP; improving verification methodologies; leading teams; managing schedules; and mentoring junior engineers. The role is full-time onsite and requires a current Secret clearance or eligibility to obtain one.