Lead STA Solutions Engineer

Posted 2 Days Ago
Be an Early Applicant
San Jose, CA
100K-186K Annually
Senior level
Cloud • Hardware • Software • Semiconductor
The Role
The Sr. Principal STA Solutions Engineer will lead and execute technical campaigns, performing static timing analysis, ECO flows, and other deliverables. The role also involves working with Cadence tools, executing timing signoff campaigns, and delivering technical training.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Overview:

Individual will be leading and executing technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should be able to efficiently work with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc.

Job Responsibilities:

· Perform Static timing analysis, glitch, noise analysis, extraction using Cadence Signoff tools. Executing and delivering on various aspects of Timing analysis flows, ECO flows, Power/EMIR, CAD tools and methodologies.

· Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows.

· Work efficiently with R&D and customer to enable various timing analysis & ECO flows.

· Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs.

· Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction, power and UPF/CPF concepts.

· Execute and lead Tempus timing signoff campaigns at existing and new customers.

· Automation of flows using scripting languages (Perl, Tcl, python).

· Deliver technical trainings and seminars within Cadence and customer sites.

Requirement :

  • 12 years experience with Bachelors in Engineering or 10 years experience + Master in related field of VLSI, Semiconductor, Electrical or Computer Engineering.
  • Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction.
  • Good understanding of Cadence Tools & flows like Tempus, Innovus or equivalent.
  • Have basic understanding of Place and route, power analysis.

Related tools/Keywords; PrimeTime, STA, Quantus

#LI-MA1

The annual salary range for California is $100,100 to $185,900. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Perl
Python
Tcl
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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