Senior Staff Analog Circuit Design Engineer - SerDes

Job Details:

Job Description: We are seeking a highly motivated and skilled Senior Staff Analog Design Engineer to contribute to the design, implementation, and validation of advanced analog and mixed-signal circuits for high-speed (112G and 224G) SerDes applications.In this role, you will participate in the definition, design, and verification of high-performance analog blocks and subsystems, collaborating closely with system architects, digital designers, and layout engineers. The ideal candidate is self-driven, detail-oriented, and passionate about analog design in high-speed communication systems.You will engage in technical discussions, contribute to design reviews, and play an active role in post-silicon validation and performance optimization. The position also involves providing guidance to layout engineers and mentoring junior analog designers as needed. Strong problem-solving skills, teamwork, and a willingness to share knowledge and collaborate across disciplines are essential.This role offers an opportunity to develop innovative designs and be part of a highly experienced SerDes team focused on delivering next-generation high-speed interconnect solutions.

Qualifications:

Minimum Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, or a related field.

• 5+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications.

• Proven experience in one or more of the following domains: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.

• Familiarity with high-speed communication standards such as PCIe (Gen4/Gen5) and Ethernet (100G/400G).

• Strong understanding of core analog design principles, including noise, linearity, matching, and stability.

• Hands-on experience with advanced FinFET CMOS process technologies.

• Proficiency with analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.

• Experience supporting silicon validation, lab measurements, and debug of analog circuits.

• Good communication and documentation skills, with a collaborative and proactive work style.

Preferred Qualifications

• Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline.

• 7+ years of experience in analog design for high-speed SerDes applications.

• In-depth understanding of transmitter and receiver design, CDR loops, and equalization techniques.

• Exposure to next-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD.

• Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl).

• Familiarity with signal integrity concepts, channel modeling, and system-level link analysis; Familiarity with inductor modelling

• Demonstrated ability to work effectively in cross-functional teams and contribute to technical reviews.

• Strong analytical thinking, hands-on debugging skills, and an eagerness to learn and share expertise within the team.

          

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:As a member of the Chief Technology Office, Artificial Intelligence, and Network and Edge Group (CTO AI NEX), you will be committed to strategically penetrating the AI market by delivering disruptive and transformative solutions. Your focus will be on leveraging technology innovation and incubation to drive commercial success, ensuring that advancements create significant value. The team is dedicated to driving the software-defined transformation of the world's networks profitably, setting new standards for efficiency and connectivity. Through these priorities, you aim to lead the way in technological evolution and redefine the future of global networks.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.