Structural Design Graduate Intern

| Phoenix – Mesa – Scottsdale, AZ
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Job Description
The Design Engineering Group (DEG) is looking for an intern in Structural / Physical Design supporting test chip design. The Test Chip Group integrates next generation IP on the latest process nodes enabling post silicon validation of critical systems before they are integrated in System on Chip (SoC) products. As an intern in this group, you would be working with a senior group of Structural Design engineers. Being a small group with quick turnaround times, you would be exposed to large parts of the SoC / ASIC design flow and many of the engineers that take RTL all the way to completed layout for manufacturing. In this role you would working the Synopsys Fusion Compiler software tool on Automated Place and Route tasks or signoff capabilities such Layout Verification, Extraction, and Static Timing Analysis.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Behavioral: Team player Self-motivated and curious Good communication skills Strong analytical skills Minimum Requirements: Junior or Senior in Electrical Engineering, Computer Engineering, or Computer Science Major Completed basic digital logic design and programming courses Experience with Linux Experience with Electronic Design Automation Tools / Computer Aided Design Preferred Requirements: TCL / Perl / Python Scripting Experience VLSI or Auto Place and Route Experience Exposure to Static Timing Analysis Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

US Intern JR0223453 Phoenix IP Engineering Group (IPG)

More Information on Intel Corporation
Intel Corporation operates in the Artificial Intelligence industry. The company is located in Santa Clara, CA, Santa Clara, CA, Folsom, CA, Hillsboro, OR, Hillsboro, OR, Irvine, CA, Chandler, AZ and Chandler, AZ. Intel Corporation was founded in 1968. It has 141941 total employees. It offers perks and benefits such as Flexible Spending Account (FSA), Disability insurance, Dental insurance, Vision insurance, Health insurance and Life insurance. To see all 70 open jobs at Intel Corporation, click here.
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