INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA and advanced design centers in Irvine, CA, San Jose, CA, Kista, Sweden, and Bangalore, India. We pioneered the industry’s lowest power Wi-Fi radio architecture for IoT applications and a revolutionary 5G platform that will transform cellular network deployments.  Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and modules with a unique value proposition for IoT applications in consumer, commercial, medical, and industrial IoT.

The candidate will be responsible for designing, developing and executing physical design implementation of low-power and high-performance SoC, including logic synthesis, floorplan and powerplan, power domain specification, place and route, clock tree synthesis, static timing analysis, IR drop analysis, EM, and physical verification in advanced technology nodes.

Key Responsibilities

• Work with the RTL and System design teams to drive the physical design of the device in early design cycle
• Design, implement and verify suitable methodology that meets the QoR goals
• Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution.
• Deliver physical design of entire SoC, complete with specification, flow and automation
• Interface with the RTL design team to drive design modifications to resolve physical design issues and implement ECOs
• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality
• Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions

Job Requirements

• Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline
• 15+ years of proven experience in physical design
• Experience in physical design and timing closure for advanced nodes
• Experience in Cadence EDA tools for physical design and verification
• Experience in floor planning, power planning, CTS specification, place & route, and timing closure
• Experience in UPF specs design and implementation
• Be able to work with cross-functional teams, IP, and EDA vendors