Senior Digital Design Engineer

| San Diego, CA
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INNOPHASE is a rapidly growing ultralow-power wireless semiconductor startup with headquarters located in San Diego, CA. We are developing complete wireless solutions with significantly differentiated power dissipation/performance tradeoffs. Our innovative technology also dramatically improves wireless product flexibility and ease-of-use for product developers. We are looking for driven candidates to join our fast-paced and motivated team. This role is an excellent opportunity for someone that enjoys a small and agile group where you can make a great impact.

In this job you will be working with a team of digital design engineers to develop novel SoC products for connectivity and communications.

The ideal candidate will be responsible for RTL coding, SoC specifications and development, constraint file development, testplan development, functional verification, static timing analysis(STA) etc.

Responsibilities

  • Develop specifications in communication and DSP area to meet marketing and system requirements.
  • Develop RTL (Verilog or VHDL), timing constraints, and detailed documentation.
  • Perform CDC/Lint checks etc.
  • Perform synthesis, STA, and logic equivalency checks. Implement ECOs.
  • RTL & gate level simulations.
  • Create verification plans.
  • Scripting with TCL, Perl, and Unix shell scripts.
  • Develop DFT.
  • Work with System, Software, RF, Analog, and Test teams and provide necessary support

Qualifications

  • BS/MS EE/CS preferred
  • 4+ years of experience RTL design, digital SoC development required
  • Experience with wireless protocols, DSP and standard digital interfaces(such as AXI, AHB)
  • Knowledge of VHDL, Verilog or SystemVerilog
  • Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
  • Understanding of synthesis, static timing, DFT and digital SoC design flows
  • Experience with ATPG, fault grading, scan, BIST, DFT a big plus
  • Knowledge of SystemVerilog assertions, checkers, and constrained random verification techniques a Plus
  • Knowledge of languages such as C/C++, Perl, Tcl or Python a plus
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