INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, Kista, Sweden, and Bangalore, India. We pioneered the industry’s lowest power Wi-Fi radio architecture for IoT applications and a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and modules with a unique value proposition for IoT and 5G applications.
The candidate will be responsible for developing micro-architecture, RTL coding, SoC specifications and architectures(communication and DSP) development and review, constraint file development, low power specification development, verification test-bench development, functional and gate level verification, and static timing analysis(STA).
- Develop specifications in communication and DSP area to meet marketing and system requirements.
- Develop RTL (Verilog or VHDL), timing constraints, and detailed documentation.
- Perform CDC/Lint checks etc.
- Perform synthesis, STA, and logic equivalency checks. Implement ECOs.
- RTL & gate level simulations.
- Create verification plans.
- Scripting with TCL, Perl, and Unix shell scripts.
- Develop DFT.
- Work with System, Software, RF, Analog, and Test teams and provide necessary support
- BS/MS EE/CS preferred
- 15+ years of experience RTL design, digital SoC development required
- Experience with wireless protocols, DSP and standard digital interfaces(such as AXI, AHB)
- Knowledge of VHDL, Verilog or SystemVerilog
- Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
- Understanding of synthesis, static timing, DFT and digital SoC design flows
- Experience with ATPG, fault grading, scan, BIST, DFT a big plus
- Knowledge of SystemVerilog assertions, checkers, and constrained random verification techniques a Plus
- Knowledge of languages such as C/C++, Perl, Tcl or Python a plus