Development Tools Software Engineering Manager
Job Description
The position offered is for a Development Tools Software Engineering Manager in the Design Rule Optimization (DRO) team of the Process Design Kit (PDK) group, within the Design Enablement (DE) organization. The role is to manage EDA Tools Software Engineers in the DRO team, ensuring regular on-time and high-quality delivery of design rule data using the Ptech tool across all of Intel's process technologies (Ptech is used in PDK automation to automatically generate DR-compliant technology files and layout test structures).
Responsibilities include staying on top of PDK schedules and PM needs, driving improvements to Ptech quality and turnaround time, building a diverse high-functioning team, developing individual staff members, developing and reconciling Objectives and Key Results (OKRs), and working with other PDK teams and design rule definition teams to address short-term issues and drive long-term solutions. Other opportunities of growth are offered in driving industry standardization of process technology expression for Intel's mature and upcoming advanced process nodes.
The DRO team works closely in partnership with Intel's technology development, EDA suppliers, PDK functional areas, Design Rule Definition, and OPC teams to optimize Intel's process technology competitiveness using traditional automation and Machine Learning (ML) techniques from highly permuted layout test case structure generation.
Important behavioral traits that are part of the requirements for this role:
- Leadership
- Customer orientation
- Problem-solving skills
- Determines objectives and sets goals
- Timely completion of long-term and/or complex projects
Qualifications
You must possess the below requirements to be initially considered for this position.
Minimum Qualifications:
Bachelors or master's in electrical engineering, Computer Science, or Computer Engineering with 6+ years of professional experience in a management or leadership role.
8+ years of experience in at least one the following:
- Custom layout
- Design Automation
- EDA tools (layout editors, PDK development, tech files, Pcells, auto-routing, etc.)
- Familiarity of advanced process node design rules
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations
US, California, Santa Clara
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
US Experienced Hire JR0211834 Phoenix Technology and Manufacturing